1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to packaging techniques for semiconductor devices that include a leadframe that utilizes columns to facilitate electrical connections.
2. Description of the Prior Art
Semiconductor devices generally include a leadframe and a bumped die attached thereto. Many of the packages are multiple pieces and rely on wire bonding as the interconnect between the die and the package. Additionally, many BGA (Ball Grid Array) substrates do not have the capability for solder balls to be pre-attached.
The prior art packages limit the ability to form thin packages. Additionally, the manufacturing processes for prior art packages are inefficient.
The present invention provides a semiconductor device that includes a die and a leadframe. The leadframe includes a die attach area on a surface of the leadframe and a plurality of columns around at least a portion of the periphery of the die attach area. The die is positioned within the die attach area and is attached thereon. The columns have a height substantially equal to solder bumps on the die when the die is on the leadframe.
In accordance with one aspect of the present invention, the leadframe comprises a Cu-based material.
In accordance with another aspect of the present invention, the leadframe includes a Nixe2x80x94Pd plating on the surface.
In accordance with a further aspect of the present invention, the columns are made up of metal studs grown from the leadframe that include a solderable coating.
In accordance with yet another aspect of the present invention, the leadframe includes notches defined in the surface around the periphery and the columns consist of solder placed in the notches.
Accordingly, the present invention provides a semiconductor device wherein the package allows for directly attaching a die onto the leadframe using conventional soft solder die attach process. When the package is used to house, for example, a discrete power MOSFET, the solder bumps on the die act as the source and gate connections to the printed circuit board (PCB) while the solderable columns on the leadframe act as the drain interconnect. The package design results in less complicated substrate processing and still maintains the package stand-off height less than 1 millimeter, which is compatible to that of existing MOSFET BGA packages.
Other features and advantages of the present invention will be understood upon reading and understanding the detailed description of the preferred exemplary embodiments found herein below, in conjunction with reference to the drawings, in which like numerals represent like elements.